On-chip Highways: 2D Interconnect for Tera-scale Processors

The ability to integrate hundreds of Intel Architecture cores into future microprocessors will help deliver the power of Moore's Law to new user interfaces and visually compelling experiences. A high performance, resilient, core-to-core interconnect will be as important for these tera-scale microprocessors as a well-designed highway grid is to moving goods and services across a country. Recently Intel demonstrated a next generation 2D interconnect prototype that provides high data bandwidth and low latencies between cores, memory and I/O. The demo also featured our -MCEMU FPGA-based many-core emulation platform developed at Intel Labs, in Braunschweig, Germany, and a 3D visual interface developed with UC Irvine.

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