![[H]ardOCP](/images/blank.gif){kind=small}
- Date:
- Thursday , October 02, 2008
- Author:
- Morry Teitelman
- Editor:
- Kyle Bennett
- Google +1
EVGA nForce 780i SLI FTW
With the introduction of the nForce 780i SLI FTW board, EVGA took the winning design of their nForce 780i SLI board and perfected it with better overall power circuitry and board cooling. Is this enough to make it competitive with the Intel chipset based solutions?
BIOS
EVGA chose to use an AwardBIOS style template for the nForce 780i SLI FTW’s BIOS. The BIOS shown below, and used in testing, is the first release of the BIOS version 00.
The Advanced BIOS Features menu contains system startup setting, including those controlling boot device access order. The Hard Disk Boot Priority submenu displays as list of detected hard disk type devices, including properly detected USB 2.0 devices.
The Integrated Peripherals menu contains settings for the onboard and integrated system devices. From the top level menu, you are able to configure the IEEE 1394 ports, USB 2.0 ports, GigE LAN ports, and audio subsystem. The IDE Function Setup submenu contains settings for configuring the IDE and SATA-2 ports, while the RAID Configuration submenu controls the integrated RAID controller operation. The SATA-2 ports themselves can be individually tied to the RAID controller, with the RAID boot BIOS displaying on system startup with a device connected to one of the RAID enabled ports.
The PCI/PnP Configurations menu contains options for controlling the system PnP and PCI related settings, including those controlling the PCI Latency Timer and the IRQ pool settings. The IRQ pool settings are accessed via the IRQ Resources submenu. The BIOS does not allow for direct manipulation of the IRQ interrupt assignments however.
The PC Health Status menu displays up to the moment statistics on all monitored system temperatures, voltages, and fan speed settings. The Dynamic Fan Control submenu contains all options for controlling the onboard fan headers. The fan headers operation can be set to manual control, or temperature based control using the SmartFan setting.
The Frequency/Voltage Control menu contains submenus for configuring the board voltage and bus speed related settings. The Dummy O.C. option controls BIOS configure overclocking settings, with the maximum automated overclocking settings allowing for a maximum of a 25% overclock. Note that you cannot configure any options within the FSB & Memory Config or System Voltages submenus with the Dummy O.C. option set to anything other than Disabled. The Load and Save settings are used to store and retrieve up to 3 user configured BIOS configuration profiles.
The System Clocks submenu contains options for chipset related configuration, as well as read-only settings displaying CPU speed and FSB related values. The CPU Multiplier and CPU N/2 Ratio options control the base CPU ratio, with the upper and lower settings determined by the currently in use CPU. The PCIe x16_1 & x16_2, MHz and PCIe x16_3, MHz options configure the speed of the PCI-Express x16 slots, with a maximum of 200MHz allowed. The SPP<->MCP Ref Clock, MHz setting configures the speed of the bus in between the North and Southbridge chipsets. The upstream and downstream link speeds are controlled via the nForce SPP <- nForce MCP and nForce SPP -> nForce MCP options, with the physical speeds determined by multiplying those ratios by the speed setting in the SPP<->MCP Ref Clock, MHz option.
The FSB & Memory Config submenu controls the base system bus and memory speeds, with memory timing related options contained under the Memory Timing Setting submenu. The SLI-Ready Memory setting configures automated overclocking of the system memory, using factory configured settings. The FSB - Memory Clock Mode option controls how the system bus speeds work, with two operation modes available, Linked and Unlinked. Linked mode operation controls the memory speed through the use of ratios based on a configured CPU FSB. The FSB (QDR), MHz option sets the CPU FSB, with a 2500MHz maximum speed allows, while the memory ratio options are set via the FSB - Memory Ratio setting. In Unlinked mode, the CPU FSB and memory speed are independently set, with the memory speed manually set via the MEM (DDR), MHz option. The memory speed can be set to a maximum of 1400MHz.
The Memory Timing Setting submenu, accessed via the link from within the FSB & Memory Config submenu, contains all configurable memory timing related settings including the following: CAS latency; RAS to CAS delay (tRCD); RAS precharge delay (tRP); active to precharge delay (tRAS); command rate; RAS to RAS delay (tRRD); row cycle time (tRC); write recovery time (tWR); write to read delay (tWTR); refresh period (tREF); and row refresh cycle time (tRFC). Note that on the memory timings listed, the numerically lower setting forces more aggressive memory operation.
The CPU Feature submenu contains all settings related to internal CPU operation: CPUID value limit; Intel SpeedStep; CPU Thermal control; C1E support; Execute Disable Bit; and Vanderpool virtualization technology. You also have the capability to disable the second, third or forth CPU cores via the named core settings.
The System Voltages submenu contains the settings for configuring all board related voltage options. The EVGA VDroop control setting configures the board voltage droop with the Without VDroop setting giving better stability while overclocked. The base CPU voltage is set via the CPU Core voltage, with a maximum voltage allowable of 2.0V. The CPU FSB setting controls the CPU FSB speed controller chip voltage, with a 1.625V maximum. The base Memory voltage can be set to a maximum of 3.40V via the Memory option. The board Northbridge chipset voltage is configurable via the nForce SPP option, with a 1.55V maximum. The Southbridge chipset voltage can be configured to a maximum 1.750V through the nForce MCP option. The HT nForce SPP <-> MCP setting configures the voltage supplied to the bus connected the North and South bridges, with a 1.55V maximum allowed. The CPU PLL setting determines the CPU power circuitry voltage, with a 1.8V maximum. The GTLREF Lane options control the voltage supplied to the bus connecting the individual memory slots and the CPU. Each memory lane can be over-volted by up to 160mV.