- Date:
- Friday , February 01, 2008
- Author:
- Morry Teitelman
- Editor:
- Kyle Bennett
- Google +1

EVGA nForce 780i SLI
The EVGA 780i SLI packs a lot of nice features under the hood, including support for the current mainstream DDR2 memory technology, and SLI using 2 or 3 NVIDIA graphics cards. Is it enough to compete with the latest Intel DDR3 board though?
BIOS
The nForce 780i SLI is built using an AwardBIOS style BIOS template. For testing, we used BIOS version 2.053.B0.
The Advanced BIOS Features menu contains various system initialization options, including those control boot device access order. The Hard Disk Boot Priority submenu shows a list of all detected hard drive type devices connected to the system at boot time. A USB 2.0 type device will show as a viable device in this menu if properly detected by the BIOS as system start time.
The Advanced Chipset Featured menu contains numerous submenus and top level options for configuring the speed and voltage related settings. The Load and Save options can be used to store and retrieve up to 3 user configured BOIS settings profiles. The NVMEM test option enables the in built NVIDIA memory test, which would run on the next system start up after being enabled.
The System Clocks submenu contains settings for controlling the chipset related speed settings. It also contains read-only options displaying the currently CPU speed and base board bus speed. The CPU multiplier option controls the base CPU ratio, which when combined with the CPU FSB setting, determines the CPU speed. The PCIe x16_3, MHz option controls the bus speed for the 3 onboard PCI Express x16 slots, with a maximum speed setting of 200 allowed. The SPP<->MCP Ref Clock, MHz option sets the bus connecting the system North and Southbridge. The upstream and downstream link speeds are controlled via the nForce SPP --> nForce MCP and nForce SPP <-- nForce MCP options.
The FSB & Memory Config submenu contains options for configuring the CPU FSB and memory speeds. The BIOS allows for 2 base operating modes controlled via the FSB – Memory Clock Mode option – Linked and Unlinked. In Linked mode, the CPU FSB is manually configured via the FSB (QDR), MHz option with a maximum speed of 2500 available for selection . The memory speed is determined via preset ratio settings within the FSB – Memory Ratio option. In unlinked mode, the CPU FSB and memory speed are independently configurable. The memory speed, in this case, is set via the MEM (DDR), MHz option with a maximum speed allowed of 1400. The SLI-Ready Memory option contains setting for BIOS controlled FSB overclocking settings. Note that this setting only affects the CPU FSB and memory speeds, voltages must still be set manually.
The Memory Timing Setting submenu, accessed via the link with the FSB & Memory Config submenu, contains all configurable memory timing related settings. The following memory timing setting are user configurable with the Memory Timing Setting option set to Expert: CAS latency; RAS to CAS delay (tRCD); RAS precharge delay (tRP); active to precharge delay (tRAS); command rate; RAS to RAS delay (shown as tRRD); row cycle time (shown as tRC); write recovery time (shown as tWR); write to read delay (shown as tWTR); and refresh period (shown as tREF). Note that on the memory timings listed, the numerically lower setting forces more aggressive memory operation.
The CPU Configuration submenu contains settings controlling internal CPU functions, as follows: CPUID value limit; Intel SpeedStep; CPU Thermal control; C1E support; Execute Disable Bit; and Vanderpool virtualization technology. You also have the capability to disable the second, third or forth CPU cores via the named core options.
The System Voltages submenu contains options for setting of all board voltages. The CPU Core option determines the CPU voltage, with a massive 1.80V allowed. The CPU FSB option sets the voltage for the CPU clock controller chip, with a maximum of 1.5V settable. The Memory options sets the memory voltage, with an upper limit of 2.5V allowable. The Southbridge voltage can be set to a 1.55V maximum via the nForce SPP option, while the Northbridge is set via the nForce MCP option with a 1.750V maximum. The voltage for the HyperTransport bus connection the North and Southbridge is controlled via the HT nForce SPP <-> MCP setting, with a voltage maximum of 1.55V allowed. The Northbridge’s auxiliary interface voltage is controlled through the nForce MCP Auxiliary option with a 1.70V ceiling. The GTLREF Lane options control the voltage supplied to the bus connecting the individual memory slots and the CPU. Each memory lane can be over-volted by 160mV.
The Integrated Peripherals menu contains options for controlling the various onboard and system integrated devices. The IEEE 1394 and audio subsystem controllers can be configured via options located in the top level menu. The USB Config submenu contains all system USB related configuration settings.
The IDE Function Setup submenu contains options for configuring the onboard IDE and SATA 2 ports. The Serial-ATA Controller option configures the operating mode of the SATA 2 ports, with all ports active when the All Enabled option is selected. The RAID Config submenu controls the integrated RAID chipset. Notice that you have the ability to individually configure SATA 2 ports to be seen or hidden from the RAID BIOS. The RAID boot BIOS will only show with drives connected to one of the RAID enabled SATA 2 ports. The eSATA Config submenu allows for setting individual SATA 2 ports to be used as eSATA ports for connecting to eSATA devices.
The PCI/PnP Configurations menu contains all system PnP related configuration settings, including an option for configuring the PCI Latency Timer. While the BIOS does not allow for individual IRQ interrupt assignment, the board IRQ’s can be given a pool assignment via the IRQ Resources submenu.
The System Monitor menu contains real-time statistics on all BIOS monitored device temperatures, board voltages, and connect fan speeds. The Dynamic Fan Control submenu contains settings for controlling the behavior of the onboard fan headers. The fans can be set to use SmartFan control, in which an upper and lower device temperature is used to determine fan speed, or manual control, where the fan runs at a settable static speed.
